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128Kx8 Autostore nvSRAM
FEATURES
* 25, 35, 45 ns Read Access & R/W Cycle Time * Unlimited Read/Write Endurance * Automatic Non-volatile STORE on Power Loss * Non-Volatile STORE Under Hardware or Software Control * Automatic RECALL to SRAM on Power Up * Unlimited RECALL Cycles * 200K STORE Cycles * 20-Year Non-volatile Data Retention * Single 3.0V + 20%, -10% Operation * Commercial and Industrial Temperatures * Small Footprint SOIC & SSOP Packages (RoHSCompliant)
STK14CA8
DESCRIPTION
The Simtek STK14CA8 is a 1Mb fast static RAM with a non-volatile Quantum Trap storage element included with each memory cell. The SRAM provides the fast access & cycle times, ease of use and unlimited read & write endurance of a normal SRAM. Data transfers automatically to the non-volatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control. The Simtek nvSRAM is the first monolithic non-volatile memory to offer unlimited writes and reads. It is the highest performance, most reliable non-volatile memory available.
BLOCK DIAGRAM
VCC A5 A6 A7 A8 A9 A12 A13 A14 A15 A16 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Quantum Trap 1024 X 1024 ROW DECODER POWER CONTROL STORE STATIC RAM ARRAY 1024 X 1024 RECALL STORE/ RECALL CONTROL VCAP
HSB
SOFTWARE DETECT INPUT BUFFERS COLUMN I/O COLUMN DEC
A15 - A0
A0 A1 A2 A3 A4 A10 A11
G E W
This product conforms to specifications per the terms of Simtek standard warranty. The product has completed Simtek internal qualification testing and has reached production status.
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STK14CA8
PACKAGES
VCAP A16 A14 A12 A7 A6 A5 NC A4 NC NC NC VSS NC NC DQ0 A3 A2 A1 A0 DQ1 DQ2 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC A15 HSB W A13 A8 A9 NC A11 NC NC NC VSS NC NC DQ6 G A10 E DQ7 DQ5 DQ4
VCAP A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 HSB W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
32-Pin SOIC
48-Pin SSOP Relative PCB area usage. See page 17 for detailed package size specifications.
PIN DESCRIPTIONS
Pin Name A16-A0 DQ7-DQ0 E W G VCC HSB Input I/O Input Input Input Power Supply I/O I/O Description Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array Data: Bi-directional 8-bit data bus for accessing the nvSRAM Chip Enable: The active low E input selects the device Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the falling edge of E Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high caused the DQ pins to tri-state. Power: 3.0V, +20%, -10% Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not connected. (Connection Optional). Autostore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile storage elements. Ground Unlabeled pins have no internal connections.
VCAP VSS NC
Power Supply Power Supply No Connect
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SSOP
DQ3 VCC
SOIC
STK14CA8
ABSOLUTE MAXIMUM RATINGS
Voltage on Input Relative to Ground . . . . . . . . . . . . . -0.5V to 4.1V Voltage on Input Relative to VSS . . . . . . . . . .-0.5V to (VCC + 0.5V) Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . .-0.5V to (VCC + 0.5V) Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .-55C to 125C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .-55C to 140C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to 150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Note a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS
jc 5.4 C/W; ja 44.3 [0fpm], 37.9 [200fpm], 35.1 C/W [500fpm].
RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS
jc 6.2 C/W; ja 51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm].
DC CHARACTERISTICS
COMMERCIAL SYMBOL ICC1 PARAMETER MIN Average VCC Current 65 55 50 70 60 55 mA mA mA MAX MIN MAX INDUSTRIAL UNITS
(VCC = 2.7V-3.6V)
NOTES
tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns Dependent on output loading and cycle rate. Values obtained without output loads. All Inputs Don't Care, VCC = max Average current for duration of STORE cycle (tSTORE) W (V CC - 0.2V) All Other Inputs Cycling at CMOS Levels Dependent on output loading and cycle rate. Values obtained without output loads. All Inputs Don't Care Average current for duration of STORE cycle (tSTORE) E (VCC -0.2V) All Others VIN 0.2V or (VCC-0.2V) Standby current level after nonvolatile cycle complete VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G VIH All Inputs All Inputs IOUT = - 2mA IOUT = 4mA
ICC2
Average VCC Current during STORE 3 3 mA
ICC3
Average VCC Current at tAVAV = 200ns 3V, 25C, Typical 10 10 mA
ICC4
Average VCAP Current during AutoStore Cycle VCC Standby Current (Standby, Stable CMOS Levels)
3
3
mA
ISB
3
3
mA
IILK IOLK VIH VIL VOH VOL TA VCC VCAP NVC DATAR
Input Leakage Current Off-State Output Leakage Current Input Logic "1" Voltage Input Logic "0" Voltage Output Logic "1" Voltage Output Logic "0" Voltage Operating Temperature Operating Voltage Storage Capacitance Nonvolatile STORE operations Data Retention 0 2.7 17 200 20 2.0 VSS -0.5 2.4
1 1 VCC + 0.3 0.8 2.0 VSS -0.5 2.4 0.4 70 3.6 120 -40 2.7 17 200 20
1 1 VCC + 0.3 0.8
A A V V V
0.4 85 3.6 120
V C V F K Years
3.3V + 0.3V Between VCAP pin and VSS, 5V rated.
@ 55 deg C
Note: The HSB pin has IOUT=-10 uA for VOH of 2.4 V, this parameter is characterized but not tested.
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STK14CA8
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 and 2
CAPACITANCEb
SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance
(TA = 25C, f = 1.0MHz)
MAX 7 7 UNITS pF pF CONDITIONS V = 0 to 3V V = 0 to 3V
Note b: These parameters are guaranteed but not tested.
3.0V
577 Ohms OUTPUT 789 Ohms 30 pF INCLUDING SCOPE AND FIXTURE
Figure 1: AC Output Loading
3.0V
577 Ohms OUTPUT 789 Ohms 5 pF INCLUDING SCOPE AND FIXTURE
Figure 2: AC Output Loading for Tristate Specs (tHZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ)
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STK14CA8
SRAM READ CYCLES #1 & #2
SYMBOLS NO. #1 1 2 3 4 5 6 7 8 9 10 11 tAXQXd tAVAVc tAVQVd #2 tELQV tELEH
c d
STK14CA8-25 PARAMETER Alt. tACS tRC tAA tOE Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold after Address Change Address Change or Chip Enable to Output Active Address Change or Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby 0 25 0 10 3 3 10 25 25 12 MIN MAX 25
STK14CA8-35 MIN MAX 35 35 35 15 3 3 13 0 13 0 35
STK14CA8-45 UNITS MIN MAX 45 45 45 20 3 3 15 0 15 0 45 ns ns ns ns ns ns ns ns ns ns ns
tAVQV
tGLQV tAXQX tELQX tEHQZe tGLQX tGHQZ
e b d
tOH tLZ tHZ tOLZ tOHZ tPA tPS
tELICCH
tEHICCLb
Note c: Note d: Note e: Note f:
W must be high during SRAM READ cycles. Device is continuously selected with E and G both low Measured 200mV from steady state output voltage. HSB must remain high during READ and WRITE cycles.
SRAM READ CYCLE #1: Address Controlledc,d,f
2 tAVAV ADDRESS 5 tAXQX DQ (DATA OUT)
DATA VALID
3 tAVQV
SRAM READ CYCLE #2: E and G Controlledc,f
ADDR ESS t E LE H 1 tEL Q V
2 29
tEHAX 11 tEHI CC L 7 tEHQ Z
E
27
6 t ELQ X
G
t AV QV 4 8 tG L Q X t G L QV 9 tGH Q Z
3
DQ (D ATA OUT) 10 tELI CC H
AC T IVE
DAT A VAL ID
ICC
ST AND BY
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STK14CA8
SRAM WRITE CYCLES #1 & #2
SYMBOLS NO. #1 #2 Alt. PARAMETER MIN MAX MIN MAX MIN MAX STK14CA8-25 STK14CA8-35 STK14CA8-45 UNITS
12 13 14 15 16 17 18 19 20 21
tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX t WLQZ
e, g
tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX
tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW
Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold after End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold after End of Write Write Enable to Output Disable Output Active after End of Write
25 20 20 10 0 20 0 0 10 3
35 25 25 12 0 25 0 0 13 3
45 30 30 15 0 30 0 0 15 3
ns ns ns ns ns ns ns ns ns ns
tWHQX
Note g: If W is low when E goes low, the outputs remain in the high-impedance state. Note h: E or W must be VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledg,h
12 tAVAV ADDRESS 14 tELWH E 17 tAVWH 13 tWLWH 15 tDVWH DATA IN 20 tWLQZ DATA OUT
PREVIOUS DATA HIGH IMPEDANCE DATA VALID
19 tWHAX
18 tAVWL W
16 tWHDX
21 tWHQX
SRAM WRITE CYCLE #2: E Controlledg,h
12 tAVAV ADDRESS 18 tAVEL E 14 tELEH 19 tEHAX
17 tAVEH W
13 tWLEH 15 tDVEH 16 tEHDX
DATA VALID HIGH IMPEDANCE
DATA IN DATA OUT
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STK14CA8
AutoStore/POWER-UP RECALL
SYMBOLS NO. Standard Alternate PARAMETER MIN MAX STK14CA8 UNITS NOTES
22 23 24 25
tHRECALL tSTORE VSWITCH VCCRISE tHLHZ
Power-up RECALL Duration
STORE Cycle Duration
20 12.5 2.65 150
ms ms V
s
i j,k
Low Voltage Trigger Level VCC Rise Time
Note i: tHRECALL starts from the time VCC rises above VSWITCH Note j: If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place Note k: Industrial Grade Devices require 15 ms MAX.
AutoStore/POWER-UP RECALL
STORE occurs only if a SRAM write has happened. No STORE occurs without at least one SRAM write.
VCC 24 VSWITCH
25 tVCCRISE
AutoStoreTM
23 tSTORE 23 tSTORE
POWER-UP RECALL
22 tHRECALL
22 tHRECALL
Read & Write Inhibited
POWER-UP RECALL
BROWN OUT TM AutoStore
POWER-UP RECALL
POWER DOWN TM AutoStore
Note: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below VSWITCH
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STK14CA8
SOFTWARE-CONTROLLED STORE/RECALL CYCLEl,m
Symbols NO. E Cont G Cont Alternate PARAMETER MIN STORE/RECALL Initiation Cycle Time MAX MIN MAX MIN MAX STK14CA8-35 STK14CA8-35 STK14CA8-45 UNITS NOTES
26 27 28 29 30
tAVAV tAVEL tELEH tEHAX tRECALL
tAVAV tAVGL tGLGH tGHAX tRECALL
tRC tAS tCW
25 0 20 1 50
35 0 25 1 50
45 0 30 1 50
ns ns ns ns
s
m
Address Set-up Time Clock Pulse Width Address Hold Time
RECALL Duration
Note l: The software sequence is clocked on the falling edge of E controlled READs or G controlled READs Note m: The six consecutive addresses must be read in the order listed in the in the Software STORE/RECALL Mode Selection Table. W must be high during all six consecutive cycles.
SOFTWARE STORE/RECALL CYCLE: E CONTROLLEDm
26 tAVAV ADDRESS 27 tAVEL
ADDRESS #1
26 tAVAV
ADDRESS #6
E
28 tELEH
29 tEHAX
G
23 tSTORE DQ (DATA)
DATA VALID DATA VALID
/t
30
RECALL
HIGH IMPEDENCE
SOFTWARE STORE/RECALL CYCLE: G CONTROLLEDm
26 tAVAV ADDRESS
ADDRESS #1
26 tAVAV
ADDRESS #6
E
27 tAVGL
28 tGLGH
G
23 tSTORE
/
29 tGHAX DQ (DATA)
DATA VALID DATA VALID
30 tRECALL
HIGH IMPEDENCE
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STK14CA8
HARDWARE STORE CYCLE
SYMBOLS PARAMETER Standard Alternate MIN MAX STK14CA8 UNITS NOTES
31 1 32 2
tDELAY tHLHX
tHLQZ
Hardware STORE to SRAM Disabled Hardware STORE Pulse Width
1 15
70
s
n
ns
Note n: On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read/write cycles to complete
HARDWARE STORE CYCLE
32 tHLHX
HSB (IN)
23 tSTORE
HSB (OUT)
31 tDELAY DQ (DATA OUT)
SRAM Enabled SRAM Enabled
Soft Sequence Commands
NO. SYMBOLS Standard PARAMETER STK14 CA8 MIN Soft Sequence Processing Time MAX UNITS NOTES
1 34
tSS
70
s
o,p
Notes: o: This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command. p: Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.
34 tSS Soft Sequence Command ADDRESS
ADDRESS #1 ADDRESS #6
34 tSS Soft Sequence Command
ADDRESS #1 ADDRESS #6
Vcc
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STK14CA8
MODE SELECTION
E
H L L
W
X H L
G
X L X
A16-A0
X X X 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x08B45 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x04B46 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x08FC0 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x04C63
Mode
Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Store Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall
I/O
Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z
Power
Standby Active Active
Notes
L
H
L
Active
q,r,s
L
H
L
Active
q,r,s
L
H
L
Active
q,r,s
ICC2
L
H
L
Active
q,r,s
Notes q: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. r: While there are 17 addresses on the STK14CA8, only the lower 16 are used to control software modes s: I/O state depends on the state of G. The I/O table shown assumes G low
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STK14CA8
nvSRAM OPERATION
nvSRAM
The STK14CA8 nvSRAM is made up of two functional components paired in the same physical cell. These are the SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates like a standard fast static RAM. Data in the SRAM can be transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture allows all cells to be stored and recalled in parallel. During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited. The STK14CA8 supports unlimited read and writes like a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to 200K STORE operations.
AutoStore OPERATION
The STK14CA8 stores data to nvSRAM using one of three storage operations. These three operations are Hardware Store (activated by HSB), Software Store (activated by an address sequence), and AutoStore (on power down). AutoStore operation is a unique feature of Simtek Quantum Trap technology is enabled by default on the STK14CA8. During normal operation, the device will draw current from VCC to charge a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part will automatically disconnect the VCAP pin from VCC. A STORE operation will be initiated with power provided by the VCAP capacitor. Figure 3 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to the DC CHARACTERISTICS table for the size of the capacitor. The voltage on the VCAP pin is driven to 5V by a charge pump internal to the chip. A pull up should be placed on W to hold it inactive during power up. To reduce unneeded nonvolatile stores, AutoStore and Hardware Store operations will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation
VCC
SRAM READ
The STK14CA8 performs a READ cycle whenever E and G are low while W and HSB are high. The address specified on pins A0-16 determine which of the 131,072 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E and G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high, or W and HSB is brought low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low.
10k Ohm
VCAP
VCC
VCAP
W
Figure 3. AutoStore Mode
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0.1F
STK14CA8
has taken place. The HSB signal can be monitored by the system to detect an AutoStore cycle is in progress. To initiate the software STORE cycle, the following READ sequence must be performed:
1 Read Address 2 Read Address 3 Read Address 4 Read Address 5 Read Address 6 Read Address 0x4E38 0x83E0 0x703F Valid READ Valid READ Valid READ
HARDWARE STORE (HSB) OPERATION
The STK14CA8 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin can be used to request a hardware STORE cycle. When the HSB pin is driven low, the STK14CA8 will conditionally initiate a STORE operation after tDELAY. An actual STORE cycle will only begin if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin has a very resistive pullup and is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress. This pin should be externally pulled up if it is used to drive other inputs. SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the STK14CA8 will continue to allow SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low, it will be allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high. If HSB is not used, it should be left unconnected.
0xB1C7 Valid READ 0x7C1F Valid READ 0x8FC0 Initiate STORE Cycle
Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence and that G is active. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation.
SOFTWARE RECALL
Data can be transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of E controlled or G controlled READ operations must be performed:
1 Read Address 2 Read Address 3 Read Address 4 Read Address 5 Read Address 6 Read Address 0x4E38 0x83E0 0x703F 0x4C63 Valid READ Valid READ Valid READ Initiate RECALL Cycle
0xB1C7 Valid READ 0x7C1F Valid READ
HARDWARE RECALL (POWER-UP)
During power up or after any low-power condition (VCCSOFTWARE STORE
Data can be transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK14CA8 software STORE cycle is initiated by executing sequential E controlled or G controlled READ cycles from six specific address locations in exact order. During the STORE cycle, previous data is erased and then the new data is programmed into the nonvolatile elements. Once a STORE cycle is initiated, further memory inputs and outputs are disabled until the cycle is completed.
Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM will once again be ready for READ or WRITE operations. The RECALL operation in no way alters the data in the nonvolatile storage elements.
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STK14CA8
DATA PROTECTION
The STK14CA8 protects data from corruption during low-voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The lowvoltage condition is detected when VCCNOISE CONSIDERATIONS
The STK14CA8 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1 F connected between VCC and VSS, using leads and traces that are a short as possible. As with all high-speed CMOS ICs, careful routing of power, ground, and signals will reduce circuit noise.
BEST PRACTICES
nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product's main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: * The non-volatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer's sites will sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product's firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, etc. should always program a unique NV pattern (e.g., complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. * Power up boot firmware routines should rewrite the nvSRAM into the desired state (autostore enabled, etc.). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard
LOW AVERAGE ACTIVE POWER
CMOS technology provides the STK14CA8 with the benefit of power supply current that scales with cycle time. Less current will be drawn as the memory cycle time becomes longer than 50 ns. Figure 4 shows the relationship between ICC and READ/ WRITE cycle time. Worst-case current consumption is shown for commercial temperature range, VCC=3.6V, and chip enable at maximum frequency. Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK14CA8 depends on the following items:
1 2 3 4 5 6 The duty cycle of chip enable The overall cycle rate for operations The ratio of READs to WRITEs The operating temperature The VCC Level I/O Loading
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STK14CA8
PREVENTING AUTOSTORE
The AutoStore function can be disabled by initiating an AutoStore Disable sequence. A sequence of READ operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore Disable sequence, the following sequence of E controlled or G controlled READ operations must be performed:
1 Read Address 2 Read Address 3 Read Address 4 Read Address 5 Read Address 6 Read Address 0x4E38 0x83E0 0x703F 0x8B45 Valid READ Valid READ Valid READ AutoStore Disable
0xB1C7 Valid READ 0x7C1F Valid READ
Figure 4 - Current vs Cycle Time
The AutoStore can be re-enabled by initiating an AutoStore Enable sequence. A sequence of READ operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore Enable sequence, the following sequence of E controlled or G controlled READ operations must be performed:
1 Read Address 2 Read Address 3 Read Address 4 Read Address 5 Read Address 6 Read Address 0x4E38 0x83E0 0x703F 0x4B46 Valid READ Valid READ Valid READ AutoStore Enable
0xB1C7 Valid READ 0x7C1F Valid READ
If the AutoStore function is disabled or re-enabled, a manual STORE operation (Hardware or Software) needs to be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled.
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STK14CA8
ORDERING INFORMATION STK14CA8-R F 45 I TR
Packing Option Blank=Tube TR=Tape and Reel Temperature Range Blank=Commercial (0 to +70 C) I= Industrial (-45 to +85 C) Access Time 25=25 ns 35=35 ns 45=45 ns Lead Finish F=100% Sn (Matte Tin) RoHS Compliant Package N=Plastic 32-pin 300 mil SOIC (50 mil pitch) R=Plastic 48-pin 300 mil SSOP (25 mil pitch)
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STK14CA8
ORDERING CODES
Part Number STK14CA8-NF25 STK14CA8-NF35 STK14CA8-NF45 STK14CA8-NF25TR STK14CA8-NF35TR STK14CA8-NF45TR STK14CA8-RF25 STK14CA8-RF35 STK14CA8-RF45 STK14CA8-RF25TR STK14CA8-RF35TR STK14CA8-RF45TR STK14CA8-NF25I STK14CA8-NF35I STK14CA8-NF45I STK14CA8-NF25ITR STK14CA8-NF35ITR STK14CA8-NF45ITR STK14CA8-RF25I STK14CA8-RF35I STK14CA8-RF45I STK14CA8-RF25ITR STK14CA8-RF35ITR STK14CA8-RF45ITR Description 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM Access Times 25 ns access time 35 ns access time 45 ns access time 25 ns access time 35 ns access time 45 ns access time 25 ns access time 35 ns access time 45 ns access time 25 ns access time 35 ns access time 45 ns access time 25 ns access time 35 ns access time 45 ns access time 25 ns access time 35 ns access time 45 ns access time 25 ns access time 35 ns access time 45 ns access time 25 ns access time 35 ns access time 45 ns access time Temperature Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial
SOP32-300 SOP32-300 SOP32-300 SOP32-300 SOP32-300 SOP32-300 SSOP48-300 SSOP48-300 SSOP48-300 SSOP48-300 SSOP48-300 SSOP48-300 SOP32-300 SOP32-300 SOP32-300 SOP32-300 SOP32-300 SOP32-300 SSOP48-300 SSOP48-300 SSOP48-300 SSOP48-300 SSOP48-300 SSOP48-300
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STK14CA8
PACKAGE DRAWINGS
32 Pin 300 mil SOIC
0.292 7.42 0.300 7.60
(
)
0.405 10.29 0.419 10.64
(
)
Pin 1 Index
0.810 20.57 0.822 20.88
(
)
.050 (1.27) BSC
0.026 0.66 0.032 0.81
(
)
0.090 2.29 0.100 2.54
()
0.086 0.090 2.18 ( 2.29)
0.12 0.22 0.004 0.10 0.010 0.25
0.014 0.36 0.020 0.51
()
()
DIM = INCHES DIM = mm MIN MAX
0.006 0.013
0.15 ( 0.32 ) 0.021 0.041
0 8 0.53 ( 1.04 )
o o
MIN ( MAX )
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STK14CA8
48 Pin 300 mil SSOP
TOP VIEW
N
0.620 15.75 0.630 16.00
(
) BOTTOM VIEW
0.400 0.410
( 10.16 ) 10.41
0.292 0.299 7.42 ( 7.59 ) 0.292 0.299 7.42 ( 7.59 )
.045 .055
(11.43) 13.97
1 2 3
Pin 1 indicator .045 DIA. (11.43) .020 (5.1) .035 .045
8.89 (11.43)
SIDE VIEW
0.025 (0.635) 0.008 0.0135
( 0.203) 0.343
0.095 0.110
END VIEW
0.010 0.016
( 0.25 ) 0.41
45
( 2.41) 2.79
SEATING PLANE
0.088 0.092
( 2.24 ) 2.34
SEE DETAIL A
0.620 15.75 0.630 16.00
(
)
0.008 0.016
( 0.20) 0.41
DIM = INCHES
MIN MAX
0.010 (0.25)
END VIEW
PARTING LINE
GAUGE PLANE SEATING PLANE
DIM = mm
(
MIN MAX
)
DETAIL A
0.024 0.040
( 0.61 ) 1.02
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STK14CA8
Document Revision History Rev 0.0 0.1 Date January 2003 May 2003 Change Publish New Datasheet Add 48-pin SSOP, Modify AutoStore Diagram, Update Mode Selection Table and Absolute Maximum Ratings, Added G controlled software store. Added lead-free finish
0.2 1.0
September 2003 December 2004
Parameter VCAP Min tVCCRISE ICC1 Max Com. ICC1 Max Com. ICC1 Max Com. ICC1 Max Ind. ICC1 Max Ind. ICC1 Max Ind. ICC2 Max ICC4 Max tHRECALL tSTORE tRECALL tGLQV
1.1 August 2005
Old Value New Value Notes 10uF 17uF NA 35 mA 40 mA 50 mA 35 mA 45 mA 55 mA 1.5 mA 0.5 mA 5 ms 10 ms 20 us 10 ns 150 us 50 mA 55 mA 65 mA 55 mA 60 mA 70 mA 3.0 mA 3.0 mA 20 ms 12.5 ms 40 us 12 ns 25 ns device New Spec @45 ns access @35 ns access @25 ns access @45 ns access @35 ns access @25 ns access Com. & Ind. Com. & Ind.
Parameter ICC3 Max Com. ICC3 Max Ind. ISB Max Com. ISB Max Ind. tRECALL tSTORE NVc
Old Value New Value 5 mA 10 mA 5 mA 2 mA 2 mA 40 us 12.5 ms 1x10
6
Notes
10 mA 3 mA 3 mA 50 us 15 ms 5x10
5
Soft Recall Industrial Grade Only Contact Simtek For Details
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STK14CA8
Rev 1.2 1.3 Date September 2005 December 2005
Parameter tRECALL tSS Old Value 60 us Undefined 100 Years at Unspecified Temperature New Value 50 us 70 us 20 Years @ Max Temperature Notes Typographical Error In Datasheet
Change Added an Extended Temperature Range device tested from -55 degree C to +85 degree C
DATAR
New Data Retention Specification
1.4 1.5
March 2006 February 2007
Removed Lead Plated Lead Finish
Parameter NVC DATAR VSWITCH Min. IOUT (HSB) tELAX, tGLAX tEHAX, tGHAX tDELAY Max. tHLBL tSS VCAP Max
Old Value 500K 20 Years @ 85 C 2.55 V
Notes New Nonvolatile 200K Store Cycle Spec 20 Years @ New Data Retention 55 C Spec No Min. Spec Not Specified Before Removed 1 ns New Spec 70 us New Spec Spec Not Required 70 uS Max. Typo 120 uF Supports Upgrades From 14C88-3 -10 uA
New Value
20 ns
300ns 70 uS Min. 57 uF
Deleted -G Extended Temperature Option Added tape and reel ordering option Added product order code listing Added package drawings Reformatted Entire Document
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STK14CA8
Rev 2.0 Date January 2008 Change page 3: added thermal characteristics. page 5: in the SRAM Read Cycles #1 and #2 table, revised parameter description for tELQX and tEHQZ and changed Symbol #2 to tELEH for Read Cycle Time; updated SRAM Read Cycle #2 timing diagram and changed title to add G controlled. page 8: revised the notes below the Software-Controlled Store/Recall Cycle diagram. page 10: in the Mode Selection table, changed column to A16-A0. In the values in this column, added a zero after each instance of "0x." On fifth row, changed AutoStore Enable value to 0x04B46. page 11: under AutoStore Operation, revised text to read: "Refer to the DC CHARACTERISTICS table for the size of the capacitor." page 12: under Hardware Store (HSB) Operation, revised first paragraph to read "The HSB pin has a very resistive pullup..." page 13: added best practices section. page 16: added access times column to the Ordering Codes. 2.1 January 2008 Corrected pin assignments in package drawings on page 2.
SIMTEK STK14CA8 Datasheet, January 2008 Copyright 2008, Simtek Corporation. All rights reserved. This datasheet may only be printed for the expressed use of Simtek Customers. No part of the datasheet may be reproduced in any other form or means without the express written permission from Simtek Corporation. The information contained in this publication is believed to be accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein constitutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark, or other proprietary right.
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